8:30-9:00

10:00-10:30

Intelligent Monitoring of Communications Applications Hosted on the ‘Outside’
With an increasing number of communications applications hosted outside a given organization’s domain, organizations can no longer rely on internal servers to provide communications logs or forensics information.  In these cases, the best solution is to use intelligent probes to monitor the communications at the application level and generate the desired log information (e.g., CRD/IPDR).  This session will explore the basic concepts and look at several applications of this approach, including monitoring secure networks for internet threat activity as well as monitoring communications hosted outside of national domains.
Kevin Graves, CTO, IP Fabrics

10:30-11:00

DPI and Intelligent Probes for Lawful Interception, Network Security and Traffic Enforcement
In today’s rapidly evolving IP world, managing cyber security threats is rife with challenges.  In addition to the ever-expanding sources of threats, they are now dynamic in nature with malicious content embedded deeper within the communications flows.  Today’s cyber security solutions need more comprehensive and intelligent data inspection capabilities as well as proactive integration to other threat mitigation systems.  Session attendees will learn how next-generation deep packet inspection-enabled intelligent probes significantly strengthen threat mitigation solutions, delivering increased cyber security protection to service providers and government agencies alike
Joel Ebrahimi, Solutions Engineer, Bivio Networks

12:00-12:30

Evolving x86-Based Architectures for 40 Gbps Deep Packet Inspection Designs
As networks evolve to 10- and 40-Gigabit Ethernet, network and security application vendors require that regular expression (RegEx) and signature matching for deep packet inspection (DPI) scale to increased bandwidths.  Appliance manufacturers are frequently confronted with the decision to integrate embedded RegEx hardware or leverage next generation IA/x86 CPUs for RegEx processing and DPI.  These architectures alone, however, struggle to provide the required network processing and intelligence at 40 Gbps traffic rates, leaving processing components under utilized.  To overcome these challenges a heterogeneous multicore architecture, coupling workload-specific network flow processing and x86 application and control plane processing, is required.  This architecture enables network co-processing to take responsibility for network I/O, scalable flow processing at line-rate, and intelligent flow dispatching to DPI engines.  This presentation will explore the heterogeneous architecture and describe the functions of each component by citing real-world examples and describe the functions of each component by citing real-world examples supported by quantitative CPU, throughput, and power results.
Robert Truesdall, Netronome